Semiconductor memory devices for storing data are generally classified into volatile and nonvolatile semiconductor memory devices. When power is turned off, the volatile memory devices lose their data. The nonvolatile memory devices maintain their data even when the power is turned off. As such, the nonvolatile semiconductor memory devices are widely used in applications where power is suddenly interrupted.
One nonvolatile semiconductor memory device is a flash memory device. Flash memory devices comprise electrically erasable and programmable ROM cells that are referred to as flash EEPROM cells. A flash EEPROM cell generally includes a cell transistor that has a semiconductor substrate (or bulk) of a first conductivity type (e.g., P-type), source and drain regions of a second conductivity type (e.g., N-type) spaced from each other, a floating gate for storing charges and positioned over a channel region between the source and drain regions, and a control gate positioned over the floating gate.
As will be understood by those skilled in the art, a flash memory device might contain a column-by-column array of NAND EEPROM cells having the general construction illustrated in FIGS. 11.58 and 11.59, pp. 603-04, from Semiconductor Memories by B. Price et al., published by John Wiley & Sons Ltd. (1991), which is hereby incorporated by reference.
FIG. 1 is a block diagram of a conventional flash memory device having the above-mentioned cell structure. The conventional memory device 1 includes an array 10 divided into a plurality of memory blocks BLK0-BLKi. Each of the memory blocks BLK0-BLKi includes a plurality of strings illustrated in FIG. 2. Each string is connected to a corresponding bit line BLm (m=0-i), and has a string select transistor SST, a ground select transistor GST, and a plurality of flash EEPROM cell transistors Mn (e.g., n=0-15) connected in series between the source of the string select transistor SST and the drain of the ground select transistor GST. The drain of the string select transistor SST in each string is connected to a corresponding bit line BLi, the source of the ground select transistor GST is coupled to a common source line (or a common signal line) CSL. Gates of the string select transistors SST are commonly connected to a string select line SSL and gates of the ground select transistors GST are coupled in common to a ground select line GSL. Control gates of the flash EEPROM cell transistors M0-M15 in each string are commonly coupled to a corresponding one of word lines WL0-WL15. The bit lines BL0-BLi are electrically connected to a sense amplifier circuit 18 shown in FIG. 1. As is well known to those skilled in the art, the sense amplifier circuit 18 of the NAND-type flash memory device is composed of a plurality of page buffers (not shown).
Returning to FIG. 1, the conventional NAND-type flash memory device 1 further comprises a pre-decoder circuit 12, a block select circuit 14, a drive circuit 16, an Y-pass gate circuit 20, and an input/output buffer circuit 22. The block select circuit 14 selects one of the memory blocks BLK0-BLKi responsive to signals output from the pre-decoder circuit 12, and supplies the lines SSL, WL0-WLi, and GSL of the selected memory block with drive voltages from the drive circuit 16 depending on each of program and read modes of operation.
Referring to FIG. 2, a portion of a block select circuit 14 corresponding to a memory block BLKi is illustrated. Although not shown, block select circuits associated with other memory blocks will be configured the same as those shown in FIG. 2. The block select circuit 14 is composed of a block select signal generator 15 (serving as a block select decoder) for generating a block select signal BLSELi in response to a block select address. A plurality of block select transistors BT0-BT17 have sources connected to the string select line SSL, the word lines WL0-WL15, and the ground select line GSL. Drains of the transistors BT0-BT17 are connected to drive lines SS, CG0-CG15 and GS for transferring corresponding drive voltages from the drive circuit 16. The gates of the block select transistors BT0-BT17 are coupled in common to the block select signal generator 15 to receive the block select signal BSELi. Thus, the block select transistors BT0-BT17 are simultaneously turned on/off by the block select signal BSELi.
To program an EEPROM cell transistor in a selected memory block, a block select signal BSELi will be activated high. This causes the select transistors BT0-BT17 of the block select circuit 14 (corresponding to the selected memory block) to be simultaneously turned on. On the other hand, block select signals corresponding to deselected memory blocks are deactivated, turning off the select transistors BT0-BT17 of the deselected block select circuits. As a result, the string select line SSL, the word lines WL0-WL15, and the ground select line GSL of the selected memory block are electrically coupled to corresponding drive lines SS, CG0-CG15, and GS whereas the string select line SSL, the word lines WL0-WL15, and the ground select line GSL of respective deselected memory blocks float.
During the program mode of operation, the string and ground select lines SSL and GSL, respectively, of the selected memory block are respectively driven with voltages VCC and VSS through corresponding block select transistors BS0 and BS17. A selected one (e.g., WL0) of the word lines WL0-WL15 is driven with a program voltage Vpgm (e.g., 18V) through a corresponding block select transistor (e.g., BT1) while deselected wordlines (e.g., WL1-WL15) are respectively driven with a high voltage Vpass (e.g., 8V) through corresponding block select transistors (e.g., BT2-BT16). To drive the selected word line with the program voltage Vpgm and the deselected word lines with the high voltage Vpass, a voltage of the block select signal BSELi must be set at about Vpgm+Vth (Vth is the threshold voltage of each block select transistor).
Because of the above-mentioned bias condition for the block select transistors, a voltage difference of Vth between the gate and the drain of the transistor BT1 and a voltage difference of Vpgm-Vpass+Vth between the gate and the drain of each transistor BT2-BT16 develops. However, a voltage difference of about Vpgm+Vth occurs between the gate and the drain of the block select transistor BT17 coupled to the ground select line GSL. Similarly, a voltage difference of about Vpgm occurs between the gate and the drain of the block select transistor BT0 coupled to the string select line SSL. Thus, the block select transistors BT0 and BT17 are subjected to the stress of voltage differences between Vpgm+Vth and Vpgm resulting in a decline of their characteristics. By re-programming under the bias condition above described, the block select transistors BT0 and BT17 are subjected to even greater stress than other block select transistors BT1-BT16, resulting in an even greater decline of their characteristics.